This disclosure relates in general to electronic design automation (EDA) and, more specifically, logic synthesis of a circuit involving retiming.
Retiming is a technique of logic synthesis optimization that relocates registers such as flip-flops, or memory elements more generally, in a circuit in a manner that preserves the output functionality. Retiming may be applied to achieve different purposes, such as to minimize or to meet a constraint on a worst case combinational delay and/or to minimize the number of registers. Because the movement of registers redistributes timing slack in the design, retiming may dramatically alter the relative timing criticality at any given point in the design. Paths with significant slack may become critical after retiming, and paths that are initially critical may be easily fixed.
It may therefore be beneficial to provide an early estimate of the post-retiming/sequential timing model to the synthesis operations that occur before its application. This may avoid unnecessarily improving timing of non-critical components and/or unintentionally degrading elements that are critical in the post-retiming result. It also provides the earlier optimizations an additional degree of freedom to dynamically explore various configurations that may induce different register placement.
While it is possible to formulate fully sequential timing aware optimization algorithms that as such are inherently retiming aware, such approaches are experimental and not widespread in industry at this time. A practical alternative is to inject information about the sequential criticality into an existing combinational flow. This can be accomplished by adjusting the timing model.
If a circuit design is to be retimed, the quality of the final result can be improved by adjusting the timing model of the synthesis steps prior to retiming to account for the subsequent ability to relocate the registers. Two examples of how this can be accomplished include (i) temporarily replacing some registers with virtual negative-delay buffers, mapping across multi-cycle paths, and allowing the delay to be appropriately distributed into each cycle with retiming or (ii) adjusting the timing constraints at each register (e.g., by adding an intentional clock skew) to simulate its predicted structural movement. These timing adjustments occur at the original location of the register.
A problem with both of these techniques, however, is that they are unable to account for limitations on register movement and merging due to incompatible clock, reset, voltage, or enable signals, or other features, merely by way of example. In particular, when a register is replicated during retiming and each of its copies is differently constrained, no single adjustment at its original location (e.g., to the negative delay buffer or the intentional clock skew) may correctly capture the different timing along multiple fan-in/fan-out paths.
Thus, the existing approaches to modeling incompatible registers generally limit the timing adjustment at the original register location based upon the minimum or maximum compatible movement along any fan-in/fan-out path from the register. With the minimum limit, it may be assumed that retiming can only move a register as far as it can along the most-constrained path and may therefore be over-conservative; with the maximum limit, it may be assumed that retiming can move a register as far as it can along the least-constrained path and may therefore be an over-approximation. With the over-conservative limitation of register compatibility, the less-constrained paths may appear overly timing-critical. The pre-retiming optimization may not fully exploit the ability of the subsequent retiming to balance slacks, and the quality of final result (in terms of timing, area, or any other metric of interest) may be sub-optimal. With the over-approximation of the register movement, the pre-retiming optimization may assume that retiming can compensate for a timing imbalance that it may not actually be correctable due to register compatibility. The result may be a circuit with timing violations or with sub-optimal timing; it is possible for the timing of the final result to be worse than that of the original. Intermediate bounds are also possible but simultaneously suffer from both of the above limitations.
There is thus a need for methods, systems, and apparatuses that may be used for logic synthesis that are not limited to timing adjustments at the original register locations and that may not suffer from the limitations of the existing techniques.